For the rapid progress of global Internet and the increase of the population thereof, the Internet is confronting the problem of IP address shortage, so the method of Network Address Translation (NAT) is thus developed. The principle of NAT is that the packet addresses can be translated mutually between the virtual network address and the real network address so that the host possessing virtual network address can link the Wide Area Network (WAN) through such operating mechanism.
When computers in the Local Area Network (LAN) link the Wide Area Network (WAN), the virtual network address and the real network address can be translated mutually through the apparatus possessing NAT functions, such as routers. Therefore, it only requires fewer real network addresses to make all computers in the LAN be able to link the WAN so that the requirement of the real network address can thus be reduced.
The existing NAT scheme is performed by the CPU collocated with hardware circuits. Please refer to FIG. 1, showing the NAT scheme of the prior art. In FIG. 1, the NAT scheme 100 comprises a CPU (not shown in the figure), a memory 110, and a chip 130 including a LAN MAC (media access control) circuit 120 as well as a WAN MAC circuit 125.
Wherein, when receiving the packet 150 from the WAN, the WAN MAC circuit 125 will make the packet 150 be stored in the WAN RX queue 111 of the memory 110 and inform the WAN driver of the NAT scheme 100. If the packet 150 enters the WAN RX queue 111, the WAN driver will put the packet 150 from the WAN RX queue 111 into the buffer pool 113 of the memory 110. Moreover, the WAN driver can make the packet 150 in the buffer pool 113 carry out address translation as well as CRC re-calculation and transfer the address-translated packet 150 from the WAN to the LAN.
Therefore, the LAN driver of the NAT scheme 100 can fetch the address-translated packet 150 from the buffer pool 113 to the LAN TX queue 115. And the LAN driver will inform the LAN MAC circuit 120 to fetch the address-translated packet 150 from the LAN TX queue 115 so as to output.
In the NAT scheme 100 of the prior art, the operations of the WAN driver and the LAN driver both need to be executed by the CPU, which is very complex. Only the CPU possessing the excellent operation ability can reach the biggest bandwidth under the restriction, the zero wastage of the smallest packet, followed the stipulation of IEEE802.3 in the environment of 100 MHz Ethernet. Wherein, the so-called biggest bandwidth is that the interval between the packets is equal to 96 bit time.